Two Nanometres of Nothing: What Apple's New Chip Actually Changed
SCIENCE & TECHNOLOGY · SEPTEMBER 12, 2026
On 9 September Apple announced the iPhone 18 Pro, and in the middle of the presentation said the words that matter to me more than the camera: its A20 Pro chip is built on a two-nanometre process. It is the first phone chip on TSMC's N2 node, and by most accounts the first mass-market product of any kind on it. I want to explain why that is a genuine milestone, and why the number Apple used to describe it is not a measurement of anything.
What Does "2 Nanometres" Measure?
Nothing. That is the honest answer and it has been the honest answer since roughly 2011. In the beginning the node name meant something: a "1-micron" process in the 1980s had transistor gates about a micron long, and each new generation shrank that length by about thirty percent, doubling the number of transistors per area — Moore's law as an engineering schedule. Somewhere around the 28-nanometre generation the gate length stopped shrinking on schedule, because physics started objecting, but the naming kept its rhythm. Each new node got a smaller number because that is what customers expected a new node to be called. On TSMC's "2nm" process the smallest actual dimension — the pitch between adjacent gates — is a few dozen nanometres. A silicon atom sits about half a nanometre from its neighbour. Two nanometres is four atoms. There is nothing four atoms wide on this chip and nobody at TSMC will tell you there is.
So the name is a generation label, like a model year. The right question is not "how small" but "what changed," and this time the answer is the biggest structural change in the transistor since 2011.
Why Did the Fin Have to Go?
A transistor is a switch: a channel of silicon that current can flow through, and a gate beside it whose voltage opens or closes the channel. For fifty years the gate sat on top of a flat channel — one surface of contact. As transistors shrank, the gate lost its grip: the channel was so short that current leaked through even when the gate said "off," and every leaking transistor is heat and wasted battery. The fix, which Intel announced in 2011, shipped in 2012 and everyone else followed, was to stand the channel up as a thin vertical fin and drape the gate over it, so the gate touched three sides instead of one. That is the FinFET, and every phone, laptop and data-centre chip of the last decade and a half used it.
Three sides was enough for a while. It is no longer enough. The move in N2 — and in Samsung's and Intel's competing nodes of the same generation — is to slice the fin into a stack of thin horizontal sheets and wrap the gate completely around each one: top, bottom and both sides. Four sides. The gate now surrounds the channel like a hand around a hose, and its control over the current is as complete as geometry allows. The name is gate-all-around, or nanosheet. The practical consequence is that the switch closes properly again, which means less leakage, which means the chip can either run faster at the same power or the same speed at less power.
TSMC's own figures for N2 against its previous node, N3E. Ten to fifteen percent faster at the same power; twenty-four to thirty-five percent less power at the same speed, depending on which of its own presentations you read; about fifteen percent more transistors per area, up to twenty for pure logic. Those are the foundry's claims for the process, not Apple's for the chip. Apple's claims for the A20 Pro — a graphics unit up to forty percent faster than last year's, fifty percent more memory bandwidth, a doubled neural engine — mix the process gain with everything else it redesigned, and cannot be separated back out from a keynote.
Why Is the Sheet Better Than the Fin, Beyond the Fourth Side?
Because it is adjustable. A fin's width was fixed by the lithography; you got the fin you got. A nanosheet's width can be chosen per transistor: wide sheets where you want drive current, narrow ones where you want to save power, and the designer can mix them on the same chip. TSMC sells this as a feature, and it is one — it is the first time in a long while that a new node gave chip designers a new knob rather than just a smaller version of the old ones. The other thing that got better is the memory cells. On-chip cache, the SRAM that sits next to the processor cores, had essentially stopped shrinking for two generations, which was quietly one of the worst problems in the industry because modern chips are mostly cache. N2 shrinks it again.
What Did It Cost to Get Here?
Nobody outside TSMC and Apple knows the price of an N2 wafer, but the reporting has it well above the previous node, and the reporting also has Apple taking more than half of TSMC's entire 2nm capacity for the year. That is the arrangement that has held since the A-series began: Apple pays for the first year of a new node, gets it exclusively or nearly so, and everyone else — Nvidia, AMD, Qualcomm — comes in the following year once the yields have improved and the price has come down. It is the reason an iPhone chip is usually a year ahead of anything in a data centre. It is also, for what it is worth, most of why the phone costs $1,199.
I will not turn this into an investment note; the Ledger is for that, and a chip's process node is not a stock thesis. But I will note the concentration. One foundry, one node, one lead customer, one island. Every "2nm" chip in the world this year comes out of TSMC's fabs in Taiwan, and the machines that pattern them come from one company in the Netherlands. The transistor's fourth side was an engineering achievement; the supply chain that delivers it is a single point of failure that everyone has decided to live with.
Where I Could Be Wrong
The "more than half of capacity" figure is trade-press reporting, not a disclosure by either company; treat it as plausible rather than known. The gate-length and pitch numbers are approximate and vary by which feature you measure; my point is the order of magnitude, that the label is off by a factor of ten or more from anything physical, and that holds however you count. And while I have called N2 the first mass-market gate-all-around process, Samsung shipped a nanosheet node earlier in low volume — "first at scale" is the defensible claim, and the one I mean.
Sources
- Apple Newsroom. Apple debuts iPhone 18 Pro and iPhone 18 Pro Max. 9 September 2026. apple.com
- TrendForce. TSMC reveals N2 nanosheet details: 35% power savings, 15% performance gain, densest SRAM cell yet. December 2024. trendforce.com
- Tom's Hardware. SRAM scaling isn't dead after all — TSMC's 2nm process tech claims major improvements. tomshardware.com
- AppleWorld.Today. Apple's A20 Pro is rumored to use TSMC's base N2 process. September 2026. appleworld.today